The present invention relates to a semiconductor integrated circuit having its devices formed on a substrate and isolated from each other by PN junction isolation which is used, for example, to drive alternating-current plasma displays, and which is included in electrical equipment for recharging and discharging a load capacitor with alternating current to eliminate parasitic currents induced in the differentiating circuits inherently formed in the recharging and discharging equipment.
Flat-panel displays such as alternating-current plasma-display panels and alternating-current electroluminescent displays are examples of newly developed electrical devices that use such an integrated circuit. The circuit of this display can be equivalently represented as a capacitor and is shown as a load capacitor 10 in FIG. 1. The recharging and discharging of this capacitor is controlled by two symmetrically configured driving integrated circuits 1, 2 via output terminals 15, 25. This process curtails the power consumed by the whole system, improves the image quality, enhances the reliability and reduces the cost.
One circuit consists mainly of a high-level output transistor 11, a low-level output transistor 12, a high-level diode 13, and a low-level diode 14 while the other consists primarily of a high-level output transistor 21, a low-level output transistor 22, a high-level diode 23, and a low-level diode 24. The integrated circuit 1 for driving the X-electrodes includes a control circuit 6 having a low-voltage power terminal 61, an input terminal 62, a data input terminal 63, and a clock terminal 64. The integrated circuit 2 for driving the Y-electrodes includes a control circuit 7 having a low-voltage power terminal 71, an input terminal 72, a data input terminal 73, and a clock terminal 74. In the integrated circuit 1, a high-voltage power terminal 18 is connected with the control circuit 6, the collector of the high-level output transistor 11, and the cathode of the high-level diode 13. The grounding terminal 19 is connected with the control circuit 6, the emitter of the low-level output transistor 12, and the anode of the low-level diode 14. As used herein, the terms "grounding terminal", "grounding electrode" and "reference potential electrode" refer interchangeably to internal ground or reference potential within the circuit being addressed. Similarly, in the integrated circuit 2, a high-voltage power terminal 28 is connected with the control circuit 7, the collector of the high-level output transistor 21, and the cathode of the high-level diode 23. The grounding terminal 29 is connected with the control circuit 7, the emitter of the low-level output transistor 22, and the anode of the low-level diode 24.
Referring still to FIG. 1, when the transistor 12 is caused to conduct for discharging the load capacitor 10 through the grounding terminals 19, 29, the closed loop consisting of the components 10, 15, 12, 19, 29, 24, 25, 10 forms a differentiating circuit. Therefore, the potential at the output terminal 25 of the integrated circuit 2 for driving the Y-electrodes becomes lower than the potential at the grounding terminal 29. Likewise, the potential at the output terminal 15 of the integrated circuit 1 for driving the X-electrodes can drop below the potential at the grounding terminal 19. Parasitic elements inherently formed in the integrated circuits cause parasitic currents which may be wastefully consumed as parasitic collector current, for example, from the adjacent device. Parasitic currents of this kind add to power loss and detract from the function of the system and furthermore, they may cause latch-up.
FIG. 2 shows the fundamental structure of such a semiconductor circuit employing PN junction isolation. This circuit has a P-type silicon substrate 31 on which an N-type epitaxial layer 32 is formed. NPN bipolar transistors are formed in the epitaxial layer 32. The collector of each NPN bipolar transistor is formed by an N-type collector diffusion layer 34 and the epitaxial layer 32, the diffusion layer 34 being connected to an N-type buried diffusion layer 33. P layers 35 are formed in the epitaxial layer 32. Each P layer 35 forms the base of each NPN bipolar transistor. N.sup.+ layers 36 are also formed in the epitaxial layer 32. Each N.sup.+ layer 36 forms the emitter of each NPN bipolar transistor. An oxide film 38 is provided with holes through which aluminum collector electrodes 41 and base electrodes 42 contact the collector layers 34 and the base layers 35, respectively. A grounding electrode 4 is in contact with each emitter layer 36.
The semiconductor region in which one transistor is formed is electrically isolated from the other semiconductor regions by the PN junction between the P-type substrate 31 and the epitaxial layer 32, the PN junction between the substrate 31 and the collector layer 33, and the PN junction between a P-type diffusion layer 37 and the N-type epitaxial layer 32. The diffusion layer 37 extends into the substrate 31 from the surface of the epitaxial layer 32. This isolation in the integrated circuit is called PN junction isolation. Each diode region has an anode 43 formed in the P layer 35 and a cathode 44 which is in contact with one of the corresponding N.sup.+ layers 36 in the N layer 32. The diode regions are also isolated from each other by the PN junctions between the N layer 32 and the P layers 35 formed in it.
The various parasitic elements formed in this integrated circuit are shown in FIG. 3 in dotted line portion. The operation of this semiconductor integrated circuit is controlled by a control circuit 50 having two output transistors 45, 46, a Zener diode 47, and input control terminals 48, 49. An input voltage is applied between a grounding terminal 51 and an input terminal 52 so that an output may appear between a terminal 53 on a grounded substrate and an output terminal 54. Parasitic diodes 55 due to the PN junction between the P-type substrate 31 and each N.sup.+ layer 33, as shown in FIG. 2, parasitic capacitances 56, and a parasitic NPN bipolar transistor 57 are formed in this circuit. The base of each parasitic transistor 57 is formed by the P-type substrate 31 built into the two transistors 45, 46. The collector and the emitter of each parasitic transistor 57 are formed by the N-type collector layers of both transistors. Therefore, the grounding terminal 51 of the power supply of the control circuit is placed at the same potential as the junction isolation substrate 31 via the P.sup.+ isolating layers 37 which are in contact with the grounding electrode 4 inside the holes 39 as shown in FIG. 2, in order to always reverse-bias the PN junctions for reducing the parasitic effects of the parasitic elements.
When the potential at the output terminal 54 shown in FIG. 3 becomes lower than the potential at the grounding terminal 53, it substantially follows that a forward current flows into the parasitic diodes 55. This forward current flows into the base of the parasitic PNP transistor and is wastefully consumed.
It is an object of the invention to provide a semiconductor integrated circuit which is free from the foregoing problems, prevents its differentiating circuits from hindering PN junction isolation by keeping parasitic currents from flowing, reduces the power loss of the whole system, is capable of high-speed operation, and is highly resistant to noise.